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freescale semiconductor product brief document number: pxn20pb rev. 1, 06/2011 contents ? freescale semiconductor, inc., 2011. all rights reserved. the pxn20 products are compatible 32-bit microcontrollers built on power architecture ? technology. this document describes the available features, and highli ghts important characteristics of the devices. the pxn20 products are desi gned to address the need for single chip industrial netw orking applications and are tailored to address the ne ed for high performance and high memory size while keep ing the power consumption low. their core and bus architecture offer high performance processing optimized for managing intensive data exchanges be tween different types of communication protocols. it capitalizes on the available development infrastructu re of current power architecture ? devices and will be supported with software drivers and an opera ting system to assist with users implementations. the pxn20 devices have two levels of memory hierarchy, a 32 kb unified cache, and 2 mb of internal flash. the pxn20 has 592 kb on-chip l2 sram and 1 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 pxn20 features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 pxn20 block diagram. . . . . . . . . . . . . . . . . . . . . . . 4 2.3 pxn21 block diagram. . . . . . . . . . . . . . . . . . . . . . . 5 2.4 critical performance parameters. . . . . . . . . . . . . . . 6 2.5 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 developer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pxn20 product brief 32-bit power architecture ? dual core microcontrollers for industrial networking
pxn20 product brief, rev. 1 application examples freescale semiconductor 2 the pxn21 has 128 kb on-chip l2 sram. refer to table 1 for specific memory and feature sets of the family members. 1 application examples the pxn20 can be used for a vari ety of communication applications, such as industrial gateways and process control. 2features this section describes the f eatures of the pxn20 devices. 2.1 pxn20 features table 1 provides a summary of the different member s of the pxn20 family and their features. table 1. pxn20 family feature set feature pxn20 pxn21 central processing unit (cpu) e200z650 e200z650 cache 32k, 4/8way 32k, 4/8way floating point unit (fpu) yes yes signal processing engine (spe) yes yes memory management unit (mmu) 32 entry 32 entry cpu execution speed static, 116 mhz static, 116 mhz input/output proces sor (iop) e200z0 e200z0 iop execution speed 1/2 cpu execution speed 1/2 cpu execution speed flash with ecc 2 mb 2 mb data flash block 8x16 kb 8x16 kb ram with ecc 592 kb 128 kb memory protection unit (mpu) no 16 entry direct memory access unit (edma) 16 channel 32 channel ethernet (fec) yes no medialb (mlb-dim) yes no flexray controller yes (128 message buffers) no analog-to-digital converter (adc) 36 internal channels, 10-bit supports 32 external channels 64 internal channels, 10-bit supports 32 external channels total timer i/o (emios200) 24 channels, 16-bit 32 channels, 16-bit cross trigger unit (ctu) no yes asynchronous serial interfaces (uart) 6 12 synchronous serial interfaces (spi) 4 4
features pxn20 product brief, rev. 1 freescale semiconductor 3 controller area network (can) controller 6 5 inter-integrated circuit (i 2 c) controller 4 4 frequency modulated pll (fmpll) yes yes 4 ? 40 mhz xtal oscillator yes yes 16 mhz irc oscillator yes yes 32 khz xtal oscillator yes yes 128 khz irc oscillator yes yes real time counter/ autonomous periodic interrupts (rtc/api) ye s ye s periodic interrupt timer (pit) 8 8 system timer module (stm) yes yes software watchdog timer (swt) yes yes general-purpose i/o (gpio) 155 155 clock monitor (fmpll) yes yes jtag yes yes nexus debug (only supported on emulation package) nexus3 (e200z6) nexus2+ (e200z0) nexus3 (e200z6) nexus2+ (e200z0) production package 208 mapbga 208 mapbga emulation package (for developm ent use only) 256 mapbga 256 mapbga table 1. pxn20 family feature set feature pxn20 pxn21
pxn20 product brief, rev. 1 features freescale semiconductor 4 2.2 pxn20 block diagram figure 1 shows a top-level block diagra m of the pxn20 microcontrollers. figure 1. pxn20 block diagram crossbar switch (xbar) pxn20 block diagram vle mmu (32 tlb) 32 kb cache e200z650 core fpu/spe debug jtag nexus3 (z6) nexus2+ (z0) 4/8 way 4-40 mhz xtal masters 32 khz xtal 16 mhz irc e200z0 core vle semaphores 16-ch dma mux 128 khz irc fmpll 2 mb ecsm 512 kb standby ram ecsm pbridge b 6 x uart/lin 36 x adc 24 x emios 2 x i 2 c 2 x spi 6 x can pbridge a 2 x spi 2 x i 2 c sram (ecc) flash (ecc) 80 kb ecsm sram (ecc) ethernet mlb-dim flexray? vreg controller swt stm rtc/api intc pit bam siu adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller ecc ? error correction code ecsm ? error correction status module emios ? timed input/output edma ? enhanced direct memory access controller fec ? fast ethernet controller flexray? ? flexray bus controller fmpll ? frequency-modulated phase-locked loop i 2 c ? inter-integrated circuit controller intc ? interrupt controller jtag ? joint test action group interface mlb-dim ? media local bus device interface module ndi ? nexus debug interface pbridge ? peripheral i/o bridge pit ? periodic interrupt timer rtc ? real time clock siu ? system integration unit spi ? serial peripheral interface controller stm ? system timer module swt ? software watchdog timer uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vreg ? voltage regator
features pxn20 product brief, rev. 1 freescale semiconductor 5 2.3 pxn21 block diagram figure 2 shows a top-level bloc k diagram of the pxn21. figure 2. pxn21 block diagram 2.4 critical performance parameters the critical performance parameters of the pxn20 devices feature the following: ? fully static design operation up to a maximum of 116 mhz, based on 105 ? c ambient crossbar switch (xbar) memory protection unit (mpu) pxn21 block diagram vle mmu (32 tlb) 32 kb cache e200z650 core fpu/spe jtag nexus3 (z6) nexus2+ (z0) 4/8 way 4?40 mhz xtal masters 32 khz xtal 16 mhz irc vreg controller e200z0 core vle semaphores 32-ch dma mux 128 khz irc fmpll swt stm rtc/api intc pit bam siu 2 mb ecsm 128 kb standby ram ecsm pbridge b 2 x i 2 c 2 x spi 5 x can pbridge a 4 x uart/lin 2 x spi 2 x i 2 c sram (ecc) flash (ecc) ctu debug mpu ? memory protection unit ndi ? nexus debug interface pbridge ? peripheral i/o bridge pit ? periodic interrupt timer rtc ? real time clock siu ? system integration unit spi ? serial peripheral interface controller stm ? system timer module swt ? software watchdog timer uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vreg ? voltage regulator adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller ctu ? cross triggering unit ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller emios ? timed input/output fmpll ? frequency-modulated phase-locked loop i 2 c ? inter-integrated circuit controller intc ? interrupt controller jtag ? joint test action group interface 8 x uart/lin 32 x emios 64 x adc
pxn20 product brief, rev. 1 features freescale semiconductor 6 ? temperature range ?40 to 105 c ambient temperature ? low power design ? designed for dynamic power manage ment of core and peripherals ? software-controlled cloc k gating of peripherals ? simple power domains to minimi ze leakage in low power modes ? internal voltage regulator (vreg) enables operation wi th a single input voltage ? 3.3 v / 5 v supply (nominal) ? external ballast control ? adc analog supply range 3.0 v ? 5.5 v ? low voltage detect circuit implemented ? configurable pins ? selectable pull-up, pull-down, or no pull on all gpio pins ? selectable open-drain pin 2.4.1 low power operation the pxn20 devices have one dynamic power mode and one static power mode: ? low-power modes use clock gating to halt the clock for all or part of the device ? the lowest power mode also uses power gating to automatically tu rn off the power supply to parts of the device to minimize leakage ? dynamic power mode: run ? run mode is the main operating mode where the entire device is powered and clocked and where most processing activity is done ? static power mode: sleep ? sleep mode halts the clock to th e entire device and turns off th e power to the majority of the chip in order to offer the lo west power consumption mode of the pxn20. in sleep mode the contents of the cores, on-chip peripheral registers and part of the volatile memory are not held. the device can be awakened from up to 32 i/o pins, a reset, or from an internal periodic wake-up. it is also possible to enable th e 16 mhz irc, the 4?40 mh z xtal, 128 khz irc and the 32 khz xtal. ? sleep1 mode retains 32 kb of the on-chip ram ? sleep2 mode retains the 64 kb of the on-chip ram ? sleep3 mode retains 128 kb of the on-chip ram ? fast wake-up using the on-chip 16 mhz irc allo ws rapid execution from ram on exit from low power modes ? in sleep mode, a 4 ? 40 mhz xtal can be enabled to continue to run ? in sleep mode, the 16 mhz irc can be enabled to continue to run and may be selected to clock the rtc and api ? in sleep mode, the 128 khz irc can be enabled to run and may be selected to clock the rtc and api
features pxn20 product brief, rev. 1 freescale semiconductor 7 ? in sleep mode the 32 khz xtal can be enable d to run and may be selected to clock the rtc and api ? up to 32 external pins for wake-up from low power modes ? input filters available on all wake-up pins to minimize false wakeups due to noise ? rapid exit from low power mode with fast startup internal voltage regulator 2.5 packages pxn20 family members are offered in the following package types: ? 208-ball mapbga, 1mm ball pitch, 17mm ? 17mm outline for production ? 256-ball mapbga 1m m ball pitch 17mm ? 17mm outline for emulation, providing access to full nexus port without sacrif icing gpio functionality ( not available for production) 2.6 module features the following sections provide details of the modules implemented on the pxn20 family. 2.6.1 high performance e200z650 core processor (cpu) 32-bit cpu built on power architecture ? technology ? freescale variable length encoding (vle) en hancements for code size footprint reduction ? thirty-two 64-bit genera l-purpose registers (gprs) ? memory management unit (mmu) with 32-entry fu lly-associative transl ation look-aside buffer (tlb) ? branch processing unit ? fully pipelined load/store unit ? 32 kb unified cache with line locking ? 4/8-way set associative ? two 32-bit fetches per clock ? eight-entry store buffer ? way locking ? supports assigning cache as instruction or data only on a per way basis ? supports tag and data parity ? vectored interrupt support ? very low interrupt latency ? reservation instructions for implementing read -modify-write constructs (internal sram and flash) ? signal processing engine (spe ) auxiliary processing unit (apu ) operating on 64-bit general purpose registers ? floating point
pxn20 product brief, rev. 1 features freescale semiconductor 8 ?ieee ? 754 compatible with software wrapper ? single precision in hardware; double precision with so ftware library ? conversion instructions between single precision floating point and fixed point ? wait instruction ? extensive system developmen t support through nexus debug module 2.6.2 i/o processor high performance e200z0 core (iop) the iop supports the following features: ? high performance, low cost e200z0 core pro cessor for managing peripherals and interrupts ? single issue 4-stage pipelined in-ord er execution, 32-bit power architecture ? cpu ? variable length encoding (vle), allowi ng mixed 16-bit and 32-bit instructions ? results in efficient code size footprint ? minimizes impact on performance ? branch processing acceleration us ing lookahead instruction buffer ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit genera l purpose registers (gprs) ? hardware vectored interrupt support ? reservation instructions for implem enting read-modify-write constructs ? multi-cycle divide (divw) and load multipl e (lmw) store multiple (smw) multiple class instructions, can be interrupted to pr event increases in interrupt latency ? extensive system developmen t support through nexus debug port 2.6.3 on-chip flash on-chip flash on the pxn20 devi ces features the following: ? 2 mb burst flash memory ? flash partitioning: 4 ? 16 kb; 4 ? 16 kb; 2 ? 64 kb; 2 ? 128 kb; 6 ? 256 kb ? 16 kb shadow flash blocks ? typical flash access time: 0 wait -state for buffer hits, 3 wait-s tates for page buffer miss at 116 mhz ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? dual flash ports to minimize access c ontention between main core and iop ? each port supported with separate page buffers ? flash page buffers to improve access ti me to code and data held in flash ?4 ? 128-bit page buffers with programmabl e prefetch control for flash access
features pxn20 product brief, rev. 1 freescale semiconductor 9 ? page buffers can be allocated for code-only, fixe d partitions of code a nd data, all available for any access ? censorship protection scheme to prevent flash content visibility ? ee emulation supported by small 16 kb flash blocks in main array with multiple read while write partitions ? hardware managed flash writes, erase and verify sequence ? supports flash writes using in ternal 16 mhz rc oscillator ? flash partitioning: ? error correction status ? configurable error-correcting code s (ecc) reporting for ram and flash 2.6.4 on-chip sram on-chip sram on the pxn20 fa mily features the following: ? up to 592/128 kb general purpose ram table 2. flash partitioning pxn20 2 mb flash_base + 0x0000_0000 16 kb flash_base + 0x0000_4000 16 kb flash_base + 0x0000_8000 16 kb flash_base + 0x0000_c000 16 kb flash_base + 0x0001_0000 16 kb flash_base + 0x0001_4000 16 kb flash_base + 0x0001_8000 16 kb flash_base + 0x0001_c000 16 kb flash_base + 0x0002_0000 64 kb flash_base + 0x0003_0000 64 kb flash_base + 0x0004_0000 128 kb flash_base + 0x0006_0000 128 kb flash_base + 0x0008_0000 256 kb flash_base + 0x000c_0000 256 kb flash_base + 0x0010_0000 256 kb flash_base + 0x0014_0000 256 kb flash_base + 0x0018_0000 256 kb flash_base + 0x001c_0000 256 kb shadow block 16 kb
pxn20 product brief, rev. 1 features freescale semiconductor 10 ? two ram blocks implemented on separate crossb ar ports to reduce arbi tration events for high access master to on-chip ram. ? one port with 80 kb (pxn20 only) ? one port with 512/128 kb ram ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses 2.6.5 on-chip voltage regulator (vreg) the on-chip voltage regulator in cludes the following features: ? single supply device ? 3.3 v / 5 v (nominal) input supply voltage supported ? supports i/o levels inde pendent of main supply ? mlb has separate supply pins to support down to 2.5 v (nominal) operation ? multiple i/o domains wi th separate supply pins ? low voltage detectors (lvd) supported on internal supplies ? cold crank operation suppor ted without triggering lvds 2.6.6 fast ethernet controller (fec) the fec incorporates the following features ? support for 3 different physical interfaces ? 100 mbps ieee 802.3 mii ? 10 mbps ieee 802.3 mii ? 10 mbps 7-wire interface (industry standard) ? built in fifo and dma controller ? ieee 802.3 mac (compliant with ieee 802.3 1998 edition) ? programmable max frame length supports ieee 802.1 vl an tags and priority ? ieee 802.3 full duplex flow control ? support for full duplex operation (200 mbps thr oughput) with a system clock of 100 mhz using the external tx_clk or rx_clk ? support for full duplex operati on(100 mbps throughput) with a syst em clock of 50 mhz using the external tx_clk or rx_clk ? retransmission from transmit fifo follow ing a collision (no system bus utilization) ? automatic internal flushing of the receive fifo for runts (c ollision fragments) and address recognition rejects (no sy stem bus utilization)
features pxn20 product brief, rev. 1 freescale semiconductor 11 ? address recognition ? rmon and ieee statistics ? interrupts for network act ivity and error conditions 2.6.7 analog to digital converter module (adc) the pxn20 adc features the following: ? 10-bit a/d resolution ? 0?v dd common mode conversion range ? supports conversions speeds of up to 1 s ? internally multiplexed channels ? 10-bit ? 2 least significant bits (lsb) accu racy (tue) available for 16 channels ? 10-bit ? 3 lsb accuracy (tue) available for remaining channels ? dedicated result register availabl e for every internally muxed channel ? externally multiplexed channels ? internal control to support generation of external analog multiplexor selection ? four internal channels optio nally used to support externally multiplex inputs, providing transparent control for additional adc channels ? each of the four channels supports up to 8 externally muxed inputs ? three independently configurable sample and conversion times fo r high occurrence channels, internally muxed channels and externally muxed channels ? right-aligned result format ? support for one-shot, scan and injection conversion modes ? traceability of each channels with conversion result. ? injection mode status bit implemented on adjacent 16-bit register for each result ? independently configurable parameters for channels: ?offset refresh ? sampling ? cross triggering support (pxn21 only) ? internal conversion triggering from periodic interrupt time r (pit) or timed i/o module (emios200) via cross triggering unit (ctu) ? one input pin configurable as external conversion trigger source ? four configurable analog comparator channels offering range comparison with triggered alarm ? supports operation of adc using internal 16 mhz rc oscillator ? all unused analog pins availa ble as general purpose input pins ? selected unused analog pins availa ble as general purpose output pins ? power-down mode ? supports for dma transfer of results
pxn20 product brief, rev. 1 features freescale semiconductor 12 2.6.8 cross triggering unit (ctu) the ctu features the following: ? collection of 9 bit timer s with an exponential prescaler able to generate the trigger event for adc conversions ? 9-bit down counters co unting from a programmabl e start value to 0 ? different counters associated with different channel groups ? channel group is defined based on pwm channel clock ? different delay value for each emios flag/pit event ? 4-bit programmable exponential prescaler ? single cycle delayed trigger out put. trigger output is a combination of 64 input flags/events connected to different timers in the system ? maskable interrupt generation whenev er a trigger output is generated ? event configuration registers dedi cated to uc flag/triggering event ? acknowledgement signal to emios for clearing the flag ? synchronization with adc to avoid collision 2.6.9 serial communication interface module (uart) the pxn20 devices include up to two uart modul es and support uart master mode, uart slave mode and uart mode. the modules are uart state machine compli ant to the uart 1.3 and 2.0 and 2.1 specifications and handle uart frame transmission and recept ion without cpu intervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identi fier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors
features pxn20 product brief, rev. 1 freescale semiconductor 13 ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 2.6.10 controller area network module (can) the enhanced can module features the following: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while modul e remains syncronised to can bus ? transmit features ? arbitration scheme according to message id , message buffer numbe r or local priority ? internal arbitration to guarantee no inner priority inversion ? multiple transmit buffers to avoid outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? hardware fifo can be enabled ? 8 mailboxes can be configured to provide a 6-entry receive fifo and 8 programmable acceptance filters ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities 2.6.11 inter-ic commun ications module (i 2 c) the i 2 c module features the following: ? two-wire bi-directional serial bus for on-board communications
pxn20 product brief, rev. 1 features freescale semiconductor 14 ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection 2.6.12 serial peripheral interface module (spi) the pxn20 spi features the following: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? up to 24 chip select lines available (6 per spi module); the number avai lable at any time is dependent on package and pin multiplexing. ? up to 4 independently configurable transfer type s can be configured for each spi using the clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for de-glitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma ? serialization of selected sources (emios channels and phantom ports in siu) 2.6.13 enhanced modular input outp ut system (timers - emios200) the pxn20 family implement a scaled -down version of the emios module: ? supports timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges
features pxn20 product brief, rev. 1 freescale semiconductor 15 ? supports configurable trigger out puts for adc conversions for s ynchronization to channel output waveforms ? edge aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? up to 32 1 single action channels offering input capture and output compare functions ? up to 32 1 dual action channels offering output pulse width modulation, ? up to 13 1 output pulse width and fre quency modulation and center aligned output pwm channels with dead time. ? up to 5 1 modulus up/down counters that can be used to drive counter buses. ? dma transfer support available 2.6.14 periodic interrupt timer module (pit) the pit features the following: ? up to 8 general purpose interrupt timers ? up to 2 interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency 2.6.15 system timer module (stm) one stm supporting ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels r unning off the same up-counter ? independent interrupt source for each channel ? clocked by the main system clock ? instantiated in the same cpu clock domain ? counter can be stopped in debug mode 2.6.16 enhanced direct memory access controller (edma) the following summarizes the pxn20 im plementation of the edma controller: ? support independent 8, 16 or 32 bit single value or block transfers ? supports variable sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer interrupt or edma channel request 1. depends on pin muxing and product derivative
pxn20 product brief, rev. 1 features freescale semiconductor 16 ? each edma channel can optionally send an interr upt request to the cpu on completion of a single value or block transfer ? dma transfers possible between system memories, spis, i 2 c, adc, uart, emios200 and general purpose i/os ? programmable dma channel mux allows assignment of any dma source to any available dma channel with up to a total of 64 potential request sources. 2.6.17 crossbar switch (xbar) the crossbar switch allows concurre nt accesses between masters and sl aves, and provides these features: ? up to 6 master ports ? masters: z6 cpu, z0 cpu, edma, flexray, fec, mlb ? multiple bus slaves to enable acces s to flash, sram ports and peripherals ? multiple aips bridges to support c onnection to all pe ripheral modules ? crossbar supports consecutive transfer s from master to available slaves ? 32-bit internal address bus , 32-bit internal data bus ? user configurable priority arbitration based for masters ? temporary dynamic priority elevation for iop and dma 2.6.18 memory protection unit (mpu) the mpu provides the following features: ? supports up to 16 region descript ors for per-master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 4 concurrent read ports ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters 2.6.19 interrupt controller (intc) the pxn20 implements an interrupt cont roller that features the following: ? unique 9-bit vector for each of the 316 se parate interrupt sources (22 reserved) ? 8 software triggerable interrupt sources ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to impl ement the priority ceiling protocol for accessing shared resources. ? external high priority interrupt directly accessing the main core critical interrupt mechanism
features pxn20 product brief, rev. 1 freescale semiconductor 17 ? interrupt steering between main cpu and iop ? independent selection of any interr upt source to be routed through iop ? interrupts share same priority level between iop and cpu 2.6.20 system clocks and clock generation the following list summarizes the system clock and clock generation on the pxn20: ? system clock can be derive d from the following sources ? 4?40 mhz xtal ?fmpll ? 16 mhz irc oscillator ? programmable output clock di vider of system clock ( ? 1, ? 2, ? 4, ??????? ) ? separate programmable periphera l bus clock divider ratio ( ? 1, ? 2, ? 4, ?? ) applied to system clock ? frequency modulated phase-locked loop (fmpll) ? input clock frequency from 4 mhz to 40 mhz ? clock source from external oscillator ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter (for impr oved electromagnetic interfer ence performance and reduces number of external components required) ? on-chip crystal oscillatorsupporting 4 mhz to 40 mhz crystals ? dedicated 16 mhz inte rnal rc oscillator ? 16 mhz internal rc os cillator supports low speed code ex ecution and clocking of peripherals through selection as the system clock ? used as default clock source out of reset ? provides a clock for rapid st art-up from low power modes ? provides a clock for soft ware watchdog timer (swt) ? provides a back-up clock in the event of pll or external oscillator clock failure ? 5% accuracy over the operating temper ature range (after factory trim) ? trimming registers to support frequency ad justment with in-appl ication calibration ? dedicated internal 128 khz intern al rc oscillator fo r low power mode opera tion and self wake-up ? 5% accuracy (after factory trim) ? trimming registers to s upport improve accuracy with in-application calibration ? dedicated 32 khz external oscill ator for accurate timed wake-up
pxn20 product brief, rev. 1 features freescale semiconductor 18 2.6.21 system integration unit (siu) the siu features the following: ? up to four levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of up to 155 input/output pins (package dependent) ? all gpio pins can be independently conf igured to support pul l-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? the majority of the peripheral pins can be alternativ ely configured as bot h general purpose input or output pins. the exce ption is selected precision adc ch annels which support alternative configuration as general purpose inputs only. ? direct readback of the pin value supported on all digita l output pins through the siu ? configurable digital input filter that can be appl ied to up to 32 general pur pose input pins for noise elimination on external wakeups 2.6.22 software watchdog timer (swt) the watchdog timer on the pxn20 features the following: ? watchdog enabled out of reset with default 10 ms timeout fr om internal 16 mhz irc clock ? supports normal and windowed mode ? support for protected access to watchdog control registers with optional soft and hard locks ? soft lock allows the lock to be overridden by writing a special software code ? hard lock prevents any changes until after a reset, once enabled ? watchdog supports optional ha lting during low power modes ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset 2.6.23 boot assist module (bam) the bam is implemented as follows: ? configures device to support code download vi a can or uart and ex ecution of download routine ? multiple bootcode starting locations out of reset through implementation of sear ch for valid reset configuration halfword 2.6.24 dual-channel flexray controller (fr) the dual-channel flexray contro ller features the following: ? full implementation of flexra y protocol specification 2.1, reva ? single channel support
features pxn20 product brief, rev. 1 freescale semiconductor 19 ? flexray port a can be configured to be conne cted either to physical flexray channel a or physical flexray channel b ? flexray bus data rates of 10, 8, 5, and 2.5 mbit/s supported ? up to 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payload data stored in dedicated flexray memory ? allows for flexible and effici ent message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time ? message buffers can be configured as: ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (com bines two single buffered message buffers) ? individual message buffer r econfiguration supported ? two independent receive fifos ? one receive fifo per channel ? up to 255 entries for each fifo ? global frame id filtering, based on both value/mask filters and range filters ? global channel id filtering ? global message id filtering for dynamic segment ? size of message buffer payload data configurable from 0 up to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers a ssigned to the static segment and message buffers assigned to the dynami c segment at the same time ? support for independent internal cl ock source provided to module from a separate external 40 mhz crystal ? 1 absolute timer ? 1 timer that can be configured to absolute or relative 2.6.25 media local bus (mlb) the following summarizes the mlb configuration: ? support of 16 logical channels running at a maximum speed of 1024 fs ? transmission of commands and da ta and reception of receive status when functioning as the transmitting device associated wi th a logical channel address ? reception of commands and data and transmission as receive st atus responses when functioning as the receiving device associated with a logical channel address
pxn20 product brief, rev. 1 features freescale semiconductor 20 ? system channel command handling ? internal dma operation ? local channel buffer ram (single port ram) size of 2048 ? 36 bits words ? support for 3-pin only ? support for mlb i/o voltage specs 2.5 v (nominal) and 3.3 v (nominal) 2.6.26 real time counter (rtc) real time counter supports wake-up from low power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 sec resolution for > 1 hour period ? 1 ms resolution for 2-second period ? selectable clock sources from: ? internal 128 khz rc oscillator ? internal 16 mhz rc oscillator ? 32 khz external oscillator ? rtc supports continued operatio n through reset, count only rese t manually, or by power on reset (por) 2.6.27 jtag controller (jtagc) the jtagc is compliant with the ieee 1149.1-2001sta ndard and has the following main features: ? ieee 1149.1-2001 test acce ss port (tap) interface ? a jcomp input that provides the ability to share the tap ? a 5-bit instruction register th at supports several ieee 1149.1-2001 defined instru ctions, as well as several public and private mcu specific instructions ? three test data registers: bypass register, boundary scan register a nd a device identification register ? supporting boundary scan testing ? tap controller state machine 2.6.28 nexus development interface (ndi) the ndi module is compliant with the ieee-isto 5001-2003 standard. the fo llowing features are implemented, but only available on the 256 mapbga emulation package: ? 17-bit full duplex pin interface fo r medium and high visibility throughput ? full port mode (12 mdo) ? auxiliary input port (mcko, 12xmdo, 2xmseo, evto, evti) ? auxiliary output port ? 5 pin jtag port (jcomp, tdi, tdo, tms and tck) the npc block performs the following functions
developer support pxn20 product brief, rev. 1 freescale semiconductor 21 ? controls arbitration between e200z6 and e200z0 nexus modules to the nexus auxiliary output port ? generates full port mode indication output port ? generates mcko and freque ncy division (1/2, 1/4, 1/8). ? controls sharing of evto/evti ? enables gating of mcko when th e auxiliary output port is idle. e200z6 development support f eatures (nexus class3) ? ieee-isto 5001-2003 standa rd class 3 compliant ? program trace via branch trace messaging (btm) ? data trace via data write messaging (dwm) and data read messaging (drm). this allows the development tools to trace reads and /or writes to selected internal memory resources ? ownership via ownership trace messaging (otm ). otm facilitates owne rship trace by providing visibility of which process id or operating system task is activated ? run-time access to the e200z6 memory map via the jtag port ? watchpoint messaging ? watchpoint trigger enable of pr ogram and/or data trace messaging e200z0 development support f eatures (nexus class 2+) ? ieee-isto 5001-2003 standard clas s 2 compliant with additional cl ass 3 and 4 features available ? program trace via branch trace messaging (btm) ? ownership via ownership trace messaging (otm) ? otm facilitates ownership trace by providing vi sibility of which pr ocess id or operating system task is activated ? run-time access to the e200z6 memory map via the jtag port ? watchpoint messaging ? watchpoint trigger enable of pr ogram and/or data trace messaging capability of an event output signal from either core to generate a debug request in the other core ? all nexus port pins operate at 3.3 v levels ? nexus supports debug through reset and low power 3 developer support this family of mcus is suppported by freescale's to wer development system as well as a broad set of advanced debug and runtime software: ? codewarrior ?freemaster ?mqx ? rappid init ? rappid toolbox
pxn20 product brief, rev. 1 orderable parts freescale semiconductor 22 4 orderable parts table 3. orderable part number summary part number flash/sram package speed (mhz) mpxn2020vmg116 2 mb / 592 kb 208 mapbga (17 mm x 17 mm) 116 mpxn2120vmg116 2 mb / 128 kb 208 mapbga (17 mm x 17 mm) 116 mpx 20 note: not all options are available on all devices. see ta bl e 3 for more information. n qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 116 = 116 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 20 v temperature range mg package identifier 116 r operating frequency tape and reel indicator package identifier mg = 208 mapbga (ambient) family d = display graphics n = connectivity/network r = performance/real tiime control s=safety flash memory size 20 = 2 mb
document number: pxn20pb rev. 1 06/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved. 5 revision history table 4 summarizes revisions to this document . table 4. revision history revision (date) description rev. 1 (06/2011) initial release.

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